A New Hybrid Fault-Tolerant Architecture for Digital CMOS Circuits and Systems

نویسندگان
چکیده

برای دانلود باید عضویت طلایی داشته باشید

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

A New Hybrid Fault-Tolerant Architecture for Digital CMOS Circuits and Systems

This article may be used for research, teaching and private study purposes. Any substantial or systematic reproduction, redistribution , reselling , loan or sub-licensing, systematic supply or distribution in any form to anyone is expressly forbidden. This paper presents a new hybrid fault-tolerant architecture for robustness improvement of digital CMOS circuits and systems. It targets all kind...

متن کامل

Digital Architectures for Hybrid CMOS/Nanodevice Circuits

of the Dissertation Digital Architectures for Hybrid CMOS/Nanodevice Circuits

متن کامل

A New Design of Fault Tolerant Comparator

In this paper we have presented a new design of fault tolerant comparator with a fault free hot spare. The aim of this design is to achieve a low overhead of time and area in fault tolerant comparators. We have used hot standby technique to normal operation of the system without interrupting and dynamic recovery method in fault detection and correction. The circuit is divided to smaller modules...

متن کامل

OBIST Method for Fault Detection in CMOS Complex Digital Circuits

The paper deals with an oscillation based built-in self-test (OBIST) technique to test faults in complex CMOS digital circuits (CCDCs). It focuses on stuck-at-faults, open or short faults, parametric gate delay faults. The method converts complex CMOS digital circuit under test (CCDCUT) to an oscillator and the output pulses are measured for fix time duration. Discrepancy in the number of pulse...

متن کامل

A Hybrid Fault-Tolerant Architecture for Highly Reliable Processing Cores

Increasing vulnerability of transistors and interconnects due to scaling is continuously challenging the reliability of future microprocessors. Lifetime reliability is gaining attention over performance as a design factor even for lower-end commodity applications. In this work we present a low-power hybrid fault tolerant architecture for reliability improvement of pipelined microprocessors by p...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

ژورنال

عنوان ژورنال: Journal of Electronic Testing

سال: 2014

ISSN: 0923-8174,1573-0727

DOI: 10.1007/s10836-014-5459-3